Modern computers require various clocks operating at different frequencies to operate different individual components of individual on-board devices. In a programmable logic device (PLD), to realize various clock frequencies at the particular macro cells (or registers) of the device, previous approaches have traced multiple clock signals throughout the layout of the chip to supply the particular cells with the desired frequencies.
Modern semiconductor manufacturers typically specialize in specific component manufacturing processes in which they have expertise. For example, a manufacturer skilled in the fabrication of programmable logic devices may not necessarily be skilled in the manufacturing of phase locked loop (PLL) devices.
Personal Computer (PC) motherboard applications need a standard set of frequencies to operate. These frequencies are typically generated from a reference clock frequency. Since many designs use multiples of certain input frequencies, design engineers typically u se delay loops or counters on a PLD to achieve the various frequencies. Consequentially, the logic resources available in the programmable logic device are expended to implement this remedial frequency adjustment. As a result, either less programmable features may be implemented, or either more costly PLD complex programmable devices (CPLDs) must be implemented or field programmable gate arrays (FPGAs).
Another problem occurs when industry standards change. When standards change, design engineers typically must redesign their entire chips. For example, the peripheral connect interface (PCI) bus currently uses a bus speed of 33 MHz. It is anticipated that the industry standard for the PCI bus will be increased to 66 MHz in the future. The use of previous approaches (such as delay loops in the programming elements of the logic device) would require a significant amount of design work to upgrade to 66 MHz or any other new standard. By reducing setup times, a performance improvement may be realized.